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MSM9552/9553 IC for FM Multiplex Broadcast Reception User's Manual
Ver. 1.0
ISSUE DATE: Mar., 1998
IMPORTANT NOTICE
DARC (DAta Radio Channel), an FM multiplex broadcast technology, has been developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). Any manufacturer who intends to manufacture/sell products that utilize DARC technology needs to be licensed by NHK-ES. For detailed information on licenses, please contact: NHK Engineering Service Phone: (+81) 3-3417-4840
E2Y0001-28-30
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan
TABLE OF CONTENTS
1. GENERAL DESCRIPTION .....................................................................................1-1 2. BLOCK DIAGRAM .............................................................................................2-1
3. PIN INFORMATION .............................................................................................3-1 3.1 PIN CONFIGURATION (TOP VIEW) ..............................................................3-1 3.2 PIN DESCRIPTIONS .....................................................................................3-2 4. ELECTRICAL CHARACTERISTICS .......................................................................4-1 4.1 MSM9552 ELECTRICAL CHARACTERISTICS ............................................. 4-1 4.1.1 Absolute Maximum Ratings ...............................................................4-1 4.1.2 Recommended Operating Conditions ...............................................4-1 4.1.3 DC Characteristics .............................................................................4-2 4.1.4 AC Characteristics .............................................................................4-3 4.1.5 Filter Characteristics ..........................................................................4-4 4.2 MSM9553 ELECTRICAL CHARACTERISTICS ............................................. 4-5 4.2.1 Absolute Maximum Ratings ...............................................................4-5 4.2.2 Recommended Operating Conditions ...............................................4-5 4.2.3 DC Characteristics .............................................................................4-6 4.2.4 AC Characteristics .............................................................................4-7 4.2.5 Filter Characteristics ..........................................................................4-8 4.3 TIMING DIAGRAM ........................................................................................4-9 5. CONTROL REGISTERS ........................................................................................5-1 5.1 INTERRUPT REGISTERS ..............................................................................5-1 5.1.1 Interrupt Source .................................................................................5-1 5.1.2 INT Mask ............................................................................................5-3 5.2 RECEIVE DATA REGISTERS ........................................................................5-4 5.2.1 Receive Block Status ......................................................................... 5-4 5.2.2 Receive Data RAM Port .....................................................................5-6 5.2.3 Receive RAM, Data Accumulation Condition, and Address Clear .... 5-6 5.2.4 BIC Monitor .......................................................................................5-7 5.3 CLOCK REGENERATION REGISTERS......................................................... 5-10 5.3.1 Fixed Phase Adjustment .................................................................... 5-10 5.3.2 Bit Gate ..............................................................................................5-12 5.3.3 Integration Constant ..........................................................................5-13 5.3.4 Phase Correction Step ......................................................................5-14 5.4 BLOCK SYNCHRONIZATION REGISTERS .................................................. 5-15 5.4.1 Allowable Number of BIC Error Bits .................................................. 5-15 5.4.2 Number of Block Synchronization Backward Protection Steps ........5-16 5.4.3 Number of Block Synchronization Forward Protection Steps ........... 5-16 5.4.4 Block Synchronization Monitor ..........................................................5-17 5.4.5 Block Synchronization Set .................................................................5-18 5.4.6 Block Synchronization Clear ..............................................................5-18 5.4.7 Bit Number Monitor ........................................................................... 5-18
-i-
5.5 FRAME SYNCHRONIZATION REGISTERS .................................................. 5-19 5.5.1 Number of Frame Synchronization Backward Protection Steps ....... 5-19 5.5.2 Number of Frame Synchronization Forward Protection Steps .......... 5-19 5.5.3 Frame Synchronization Monitor......................................................... 5-20 5.5.4 Frame Synchronization Set................................................................ 5-21 5.5.5 Frame Synchronization Clear ............................................................5-21 5.5.6 Block Number Monitor ......................................................................5-21 5.5.7 Frame Format Specification ..............................................................5-23 5.6 ERROR CORRECTION REGISTERS ............................................................. 5-24 5.6.1 Internal Memory Address Counter Clear ........................................... 5-24 5.6.2 Data Transfer Port for Error Correction ............................................. 5-24 5.6.3 Error Correction Start Signal ............................................................. 5-25 5.6.4 CRC Result Indication .......................................................................5-26 5.6.5 Error Correction Result Indication .....................................................5-26 5.6.6 Majority Logic Threshold Value ......................................................... 5-27 5.6.7 Internal Address Monitor ...................................................................5-27 5.7 LAYER 4 CRC REGISTERS ..........................................................................5-31 5.7.1 Layer 4 CRC Register Clear ...............................................................5-31 5.7.2 Layer 4 CRC Data Buffer ...................................................................5-31 5.7.3 Layer 4 CRC Result Indication........................................................... 5-31 5.7.4 Layer 4 CRC Register ........................................................................5-32 5.8 ANALOG SECTION CONTROL/MONITOR REGISTER ................................ 5-34 5.9 POWER DOWN CONTROL REGISTER ........................................................5-37 5.10 TEST CONTROL REGISTERS .......................................................................5-39 5.10.1 Test Control 0 .................................................................................... 5-39 5.10.2 Test Control 1 .................................................................................... 5-39 5.11 I/O ADDRESS REGISTER .............................................................................5-42 5.12 EXTENDED PORT REGISTER .......................................................................5-43 6. EXTERNAL CONNECTION EXAMPLE .................................................................. 6-1 7. APPLICATION CIRCUIT ........................................................................................7-1 APPENDIX: INTERNATIONAL FRAME FORMAT ....................................................... Appendix-1
- ii -
Chapter 1
GENERAL DESCRIPTION
1.
GENERAL DESCRIPTION
The MSM9552 and MSM9553 are LSI devices which demodulate FM character multiplex signals in the DARC (DAta Radio Channel) format to acquire digital data. These devices operate on 5 V and 3 V, respectively. In the DARC format, baseband signals at ordinary FM broadcasting frequencies are multiplexed with 16 kbps digital data which are L-MSK-modulated at 76 kHz. Each device has a bandpass filter consisting of SCF, frame synchronization circuit, and error correction circuit, on a single chip. They allow a system for acquisition of digital data to be easily constructed by externally mounting an FM receiver tuner, microcontroller for control, and memory for temporary storage of data. The MSM9552 and MSM9553 have a simple configuration, and are equipped with only necessary functions. By making changes to software for the external microcontroller, the MSM9552 and MSM9553 meet the various requirements of FM multiplex broadcasting services to be offered in future. These devices are best suited for radio sets and information devices using FM character multiplex broadcasting, which began in Japan in October 1994. The MSM9553 is especially suitable for portable units. Features * * * * * * * * * * * * Built-in Bandpass Filter (SCF) Built-in Block Synchronization Circuit and Frame Synchronization Circuit Setting of Synchronization Protecting Stage number Regeneration of Data Clocks by Digital PLL 1T Delay Detection Built-in Error Correcting Circuit Built-in Layer 4 and Layer 2 CRC Processing Circuit International Frame Formats A (supporting a real time block), B, and C available Microcontroller Parallel Interface Clock Output for External Devices (64 kHz to 8.192 MHz selectable) Power Source: 5 V (MSM9552), 3 V (MSM9553) Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9552GS-2K, MSM9553GS-2K)
1-1
1-2
Chapter 2
BLOCK DIAGRAM
2. BLOCK DIAGRAM
AIN
LPF
Variable gain AMP
BPF (SCF)
Limiter
+ -
Clock regeneration Block synchronization Frame synchronization Timing control
Vref SG
Filter
DB2 D Q
Descrambler
WR31 >CK
Internal clock
34 Bytes RAM Read write register 2
Error correction, Layer 2 CRC
Layer 4 CRC
2-1
CLR DVDD 1T delay circuit + Data bus Address bus LPF
Frequency divider
+ -
Limiter
CPU interface
Delay Detector
Digital Signal Processor
XOUTC XOUT XTAL2 XTAL1
Data bus Address DB0-DB7 AD0-AD5
RD WR CS CLR INT
Figure 2.1 Block Diagram
2-2
Chapter 3
PIN INFORMATION
3.
3.1
,
PIN INFORMATION PIN CONFIGURATION (TOP VIEW)
42 IOWR 41 IORD 40 CLR 43 *NC 44 *NC 39 *NC 38 A5 MON 1 ADETIN AVDD 2 3 4 5 6 7 8 9 AGND SG AIN XOUTC MOUT0 MOUT1 MOUT2 10 MOUT3 11 MOUT4 12 MOUT5 13 MOUT6 14 INT 15 WR 16 *NC 17 RD 18 * Leave the NC pins (17, 39, 43, and 44) open.
37 A4
36 A3
35 A2
34 A1 33 A0 32 XOUT 31 CS 30 XTAL2 29 XTAL1 28 DVDD 27 DGND 26 DB7 25 DB6 24 DB5 23 DB4 DB3 22
DB0 19
DB1 20
44-Pin Plastic QFP
Figure 3.1 Pin Layout
3-1
DB2 21
3.2
PIN DESCRIPTIONS
Table 3.1 Pin Description Function Symbol WR RD INT CS CLR A0-A5 DB0-DB7 Pin 16 18 15 31 40 33-38 19-26 6 5 Type I I O I I I I/O I O Description Write signal to internal register. Read signal to internal register. Interrupt signal to microcontroller. When set to "L", an interrupt is generated. Chip select signal. When set to "L", the read, write, and data bus signals become effective. When set to "L", the internal register is initialized, and the IC enters power down mode. Address signal to internal register. Data bus signal to internal register. FM multiple signal input. Analog reference voltage pin. Connect a capacitor between this pin and the analog ground pin to prevent noise.
Microcontroller interface
Tuner interface
AIN SG
Analog section test
MON
1
O
Analog section waveform monitoring pin. The mode setting for the blocks in the analog section is specified by the analog section control register.
ADETIN Digital section test IORD IOWR MOUT0MOUT6 Clock XTAL1 XTAL2 XOUT XOUTC
2 41, 42 8-14 29 30 32 7
I I O I O O I
Analog signal input pin for testing. Digital section test signal input pins (pulled up internally). Digital section test signal and monitor output pins. 8.192 MHz crystal connection. 8.192 MHz crystal connection. Pin to supply variable clock (64 kHz to 8.192 MHz) to external devices. XOUT control. "L" sets XOUT output, "H" sets XOUT output inhibit. This pin is pulled up internally.
Power supply
AVDD AGND DVDD DGND
3 4 28 27
-- -- -- --
Analog power supply. Analog ground. Digital power supply. Digital ground.
3-2
Chapter 4
ELECTRICAL CHARACTERISTICS
4. 4.1 4.1.1
No. 1 2 3 4
ELECTRICAL CHARACTERISTICS MSM9552 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Symbol AVDD DVDD VI VO PD TSTG Ta = 25C, per package Ta = 25C, per output -- AVDD = DVDD Ta = 25C Condition Rating -0.3 to +7.0 V -0.3 to AVDD + 0.3 -0.3 to DVDD + 0.3 400 50 -55 to +150 mW C Unit
4.1.2
No. 1 2 3 4
Recommended Operating Conditions
Parameter Power supply voltage Crystal oscillation frequency FM multiplex signal input voltage Operating temperature Symbol AVDD DVDD fXTAL VAIN Ta Condition AVDD = DVDD -- Composite signal including multiplex signal -- Range 4.5 to 5.5 8.192 MHz 100 ppm 0.5 to 2* -40 to +85 Unit V -- VP-P C Applied Pin AVDD DVDD XTAL1, XTAL2 AIN --
* The gain of the variable gain amplifier (VGain): 1, 1.5, 2, or 3. The VGain should be adjusted to satisfy the equation: VAIN VGain = 1.5 V to 2.0 V.
4-1
4.1.3
No.
DC Characteristics
(DVDD = AVDD = 5 V 10%, DGND = AGND = 0 V, Ta = -40 to +85C) Parameter Symbol VIH Condition Min. 0.8 DVDD -- VIL -- DVDD -0.5 -- -- -2 -- -2 -- 8 -- -2 -- -- -- 0.2 DVDD -- V -- -- -- -- -- -- 35 -- -- 16 -- 0.45 2 mA IIL1 IIH2 VIL = DGND VIH = AVDD VIL = AGND VIH = DVDD DVDD = 5 V, VIL = DGND VOH = AVDD
During nonmonitoring (Hiz)
Typ. --
Max. --
Unit
Applied Pin WR, RD, XOUTC, DB0 to DB7, XTAL1, CS, A0 to A5, CLR, IORD, IOWR MOUT0 to MOUT6, INT, DB0 to DB7, XOUT WR, RD, CS, DB0 to DB7, A0 to A5, CLR
1
Input voltage
V
VOH 2 Output voltage VOL IIH1 3 Input current 1
IOH = -1 mA IOL = 2 mA VIH = DVDD
--
-- 2 mA
4
Input current 2 IIL2 -- 2 110 2
ADETIN
5 6
Input current 3 Pull-up current
IIH3 Ipull IOH IOL
mA mA
XOUTC, IORD, IOWR
7
Output off-leakage current
VOL = AGND
During nonmonitoring (Hiz) During operation, no load
mA -- 32 20 mA
MON
8
Supply current
IDD
f = 8.192 MHz During power down, no load
AVDD, DVDD mA
4-2
4.1.4
No. 1
AC Characteristics
Parameter Write setup time tSWR2 -- 60 -- -- Symbol* tSWR1 Condition -- Min. 10 Typ. -- Max. -- ns Unit Applied Pin WR, CS, A0 to A5, DB0 to DB7 WR, CS , ns ns ns ns ns ns A0 to A5, DB0 to DB7 WR RD, CS, A0 to A5 RD, CS, A0 to A5 RD WR
2 3 4 5 6 7
Write hold time Write pulse width Read setup time Read hold time Read pulse width Interval between error correction data write and write Interval between error
tHWR tWWR tSRD tHRD tWRD tIWRWRE
-- -- -- -- -- Error correction
10 65 10 10 105 250
-- -- -- -- -- --
-- -- -- -- -- --
8
correction data read and read Interval between error
tIRDRDE
Error correction
250
--
--
ns
RD
9
correction data write and read Interval between layer 4 data clear and write Interval between layer 4 data write and write Interval between layer 4 data write and read Read data output delay (1) Read data output delay (2)
tIWRRDE
Error correction
100
--
--
ns
WR, RD WR WR WR, RD RD, DB0 to DB7 RD, DB0 to DB7 INT, WR INT, DB0 INT, DB0 CLR
10 11 12 13 14
tICLRWR4 tIWRWR4 tIWRRD4 tDRD1 tDRD2 tDINTCLR tERRL tERRV tWCLR
Layer 4 CRC Layer 4 CRC Layer 4 CRC -- -- Step out interrupt Error correction interrupt -- -- --
100 4.5 4.5 -- -- 250 -- -- 200
-- -- -- -- -- -- -- -- --
-- -- -- 95 80 -- 274 2178 --
ns ms ms ns ns ns ms ms ns
15 Interrupt CLR delay 16 17 Error correction time (Horizontal direction) Error correction time (Vertical direction)
18 CLR pulse width
* See section 4.3, "TIMING DIAGRAM".
4-3
4.1.5
No. 1
Filter Characteristics
Parameter BPF pass band attenuation BPF block band attenuation (1) BPF block band attenuation (2) Symbol GAIN1 Condition 72 to 80 kHz Variable gain amplifier gain: 0 dB 0 to 53 kHz GAIN2 Variable gain amplifier gain: 0 dB 100 to 500 kHz GAIN3 Variable gain amplifier gain: 0 dB 50 -- -- dB MON 50 -- -- dB MON -- -- 3.0 dB MON Min. Typ. Max. Unit Applied Pin
2
3
4-4
4.2 4.2.1
No. 1 2 3 4
MSM9553 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Symbol AVDD DVDD VI VO PD TSTG Ta = 25C, per package Ta = 25C, per output -- AVDD = DVDD Ta = 25C Condition Rating -0.3 to +7.0 V -0.3 to AVDD + 0.3 -0.3 to DVDD + 0.3 400 50 -55 to +150 mW C Unit
4.2.2
No. 1 2 3 4
Recommended Operating Conditions
Parameter Power supply voltage Crystal oscillation frequency FM multiplex signal input voltage Operating temperature Symbol AVDD DVDD fXTAL VAIN Ta Condition AVDD = DVDD -- Composite signal including multiplex signal -- Range 2.7 to 3.3 8.192 MHz 100 ppm 0.2 to 0.9* -20 to +75 Unit V -- VP-P C Applied Pin AVDD DVDD XTAL1, XTAL2 AIN --
* The gain of the variable gain amplifier (VGain): 1, 1.5, 2, or 3. The VGain should be adjusted to satisfy the equation: VAIN VGain = 0.6 V to 0.9 V.
4-5
4.2.3
No.
DC Characteristics
(DVDD = AVDD = 3 V 10%, DGND = AGND = 0 V, Ta = -20 to +75C) Parameter Symbol VIH Condition Min. 0.8 DVDD -- VIL -- DVDD -0.5 -- -- -2 -- -2 -- 3 -- -2 -- -- -- 0.2 DVDD -- V -- -- -- -- -- -- 13 -- -- 13 -- 0.45 2 mA IIL1 IIH2 VIL = DGND VIH = AVDD VIL = AGND VIH = DVDD DVDD = 3 V, VIL = DGND VOH = AVDD
During nonmonitoring (Hiz)
Typ. --
Max. --
Unit
Applied Pin WR, RD, XOUTC, DB0 to DB7, XTAL1, CS, A0 to A5, CLR, IORD, IOWR MOUT0 to MOUT6, INT, DB0 to DB7, XOUT WR, RD, CS, DB0 to DB7, A0 to A5, CLR
1
Input voltage
V
VOH 2 Output voltage VOL IIH1 3 Input current 1
IOH = -1 mA IOL = 2 mA VIH = DVDD
--
-- 2 mA
4
Input current 2 IIL2 -- 2 50 2
ADETIN
5 6
Input current 3 Pull-up current
IIH3 Ipull IOH IOL
mA mA
XOUTC, IORD, IOWR
7
Output off-leakage current
VOL = AGND
During nonmonitoring (Hiz) During operation, no load
mA -- 22 10 mA
MON
8
Supply current
IDD
f = 8.192 MHz During power down, no load
AVDD, DVDD mA
4-6
4.2.4
No. 1
AC Characteristics
Parameter Write setup time tSWR2 -- 120 -- -- Symbol* tSWR1 Condition -- Min. 10 Typ. -- Max. -- ns Unit Applied Pin WR, CS, A0 to A5, DB0 to DB7 WR, CS , ns ns ns ns ns ns A0 to A5, DB0 to DB7 WR RD, CS, A0 to A5 RD, CS, A0 to A5 RD WR
2 3 4 5 6 7
Write hold time Write pulse width Read setup time Read hold time Read pulse width Interval between error correction data write and write Interval between error
tHWR tWWR tSRD tHRD tWRD tIWRWRE
-- -- -- -- -- Error correction
10 130 10 10 160 250
-- -- -- -- -- --
-- -- -- -- -- --
8
correction data read and read Interval between error
tIRDRDE
Error correction
250
--
--
ns
RD
9
correction data write and read Interval between layer 4 data clear and write Interval between layer 4 data write and write Interval between layer 4 data write and read Read data output delay (1) Read data output delay (2)
tIWRRDE
Error correction
100
--
--
ns
WR, RD WR WR WR, RD RD, DB0 to DB7 RD, DB0 to DB7 INT, WR INT, DB0 INT, DB0 CLR
10 11 12 13 14
tICLRWR4 tIWRWR4 tIWRRD4 tDRD1 tDRD2 tDINTCLR tERRL tERRV tWCLR
Layer 4 CRC Layer 4 CRC Layer 4 CRC -- -- Step out interrupt Error correction interrupt -- -- --
100 4.5 4.5 -- -- 250 -- -- 200
-- -- -- -- -- -- -- -- --
-- -- -- 160 160 -- 274 2178 --
ns ms ms ns ns ns ms ms ns
15 Interrupt CLR delay 16 17 Error correction time (Horizontal direction) Error correction time (Vertical direction)
18 CLR pulse width
* See section 4.3, "TIMING DIAGRAM".
4-7
4.2.5
No. 1
Filter Characteristics
Parameter BPF pass band attenuation BPF block band attenuation (1) BPF block band attenuation (2) Symbol GAIN1 Condition 72 to 80 kHz Variable gain amplifier gain: 0 dB 0 to 53 kHz GAIN2 Variable gain amplifier gain: 0 dB 100 to 500 kHz GAIN3 Variable gain amplifier gain: 0 dB 50 -- -- dB MON 50 -- -- dB MON -- -- 3.0 dB MON Min. Typ. Max. Unit Applied Pin
2
3
4-8
4.3
TIMING DIAGRAM
Address input tSWR1 CS input tSWR1 WR input tWWR tSWR2 Data bus input Figure 4.1 Write Timing tHWR tHWR tHWR
Address input tSRD CS input tSRD RD input tWRD tDRD1 Data bus output Figure 4.2 Read Timing tDRD2 tHRD tHRD
4-9
Address signal input
000H
Data signal input
XXXX01XX
WR input (INTCLR signal)
INT output
tDINTCLR
Figure 4.3 Interrupt CLR Timing
4-10
Internal memory address clear
Data write
Error correction start
Error correction
Error Internal INT read Error memory CRC correction correction address result result read read end INTCLR clear Data read
Data 33 read
Address bus 020H
021H
021H
022H
000H 000H 020H 023H 024H 021H
Don't DB0-7 = 0 Data DB3 = 1 DB3 = 1 care DB0 = 0
021H
Data
Data
Data
Data
Start signal
Data
Data
Data
Data bus
0
1
33
FF
0
33
WR RD tIWRWRE 022H DB1, 2 INT pin Error correction period
tERRL/1 horizontal block
4-11
tIWRRDE
Null
Operating
tIRDRDE
tDINTCLR
tERRV/1 vertical block (1 byte 272 words)
Figure 4.4 Error Correction Timing Diagram
CRC clear Address bus 028H CRC clear Data Data bus FF 0 029H Data 1
Data load 029H Data
n-2
CRC result read 02AH Data
n-1
DB0 = 0
WR RD tIWRWR4 tICLRWR4 Figure 4.5 Layer 4 CRC Timing Diagram tIWRRD4
4-12
Chapter 5
CONTROL REGISTERS
5. 5.1 5.1.1
CONTROL REGISTERS INTERRUPT REGISTERS Interrupt source
These registers indicate the four types of interrupt factors: (1) receive interrupt, (2) 1st horizontal error correction completion, (3) out of sync., and (4) vertical error correction/2nd horizontal error correction completion. When an interrupt occurs, "1" is written. The registers must be externally cleared after reading, however clear conditions are different for each interrupt factor. For details see Table 5.1.1. (4) (3) DB2 0 Read/ write (2) DB1 0 Read/ write (1) DB0 0 Read/ write
Address Reset value 000H Read/write (Note) (Note)
DB7 -- --
DB6 -- --
DB5 -- --
DB4 -- --
DB3 0 Read/ write
Write is used to clear the interrupt. Write = "1" : clear Write = "0" : none
5-1
Table 5.1.1 Interrupt Sources Type INT0 Receive interrupt (000H, DB0) Generation Condition At the time one block is received in a frame/block synchronization state. (Data is received only in a synchronized status; not received in an out-of-sync. state.) INT1 1st horizontal error correction completion (000H, DB1) INT2 (000H, DB2) When frame is out of Out of synchronization synchronization.
272/4 number of forward +123 18 ms -13 protection steps
Generation Cycle Every time 34 bytes are received (18 ms).
Clear Condition 1. Write DB0 = "1" to INT (000H). 2. Clear the CLR pin. (Initial setting)
At the time1st horizontal error 0.274 ms after 1st error correction is completed. correction start signal is written.
1. Write DB1 = "1" to INT (000H). 2. Clear the CLR pin. (Initial setting) 1. Write DB2 = "1" to INT (000H). 2. Clear the CLR pin.
This comes out at 10 to 12 forward protection steps is 8.
seconds when the number of (Initial setting) INT3 Vertical/horizontal 2nd error correction completion (000H, DB3) At the time error correction is When the time shown in the completed. 1. Write DB3 = "1" to INT
table below has elapsed after (000H). an error correction start signal 2. Clear the CLR pin. is written (see table below). Time Data 34 bytes 272 bytes (Initial setting)
Error Horizontal Vertical No* Yes No* Yes
0.138 ms 0.274 ms 1.090 ms 2.178 ms
*Error correction is skipped when there is no error.
5-2
5.1.2
INT Mask
This register controls interrupt generation. (1)
Address Read/write 001H (1) Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 0
DB2 0
DB1 0
DB0 0
DB0-DB3: 0: INT0-INT3 interrupt disabled 1: INT0-INT3 interrupt enabled INT0: Receive interrupt INT1: 1st horizontal error correction completion interrupt INT2: Out-of-sync interrupt INT3: Vertical/2nd horizontal error correction completion interrupt DB DB3 INT3 D Q CK
DB2
INT2 D Q INT pin CK
DB1
INT1 D Q CK
DB0 WR01 CLR
INT0 D Q CK
Figure 5.1.1 INT Mask Register
5-3
5.2 5.2.1
RECEIVE DATA REGISTERS Receive Block Status
This register indicates the status of the received block data, which consists of the following: (1) Frame Number Change, (2) Frame Number, (3) Block Synchronization Status, (4) Parity Block Indication, (5) Frame Synchronization Status, (6) Layer 2 CRC Result, and (7) Real Time Block Indication (7) (6) (5) (4) (3) (2) (1)
Address Read/write 002H (1) Read
Reset value
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
DB0: FNCHG (Frame Number Change)
0: No frame number changed 1: "1" is indicated when receive data is the first data (2nd byte) of block number 1, 14, 137, 150 for Method A, and block numbers 1, 61, 131, 191 for Method B. (2) DB1-DB2: Frame Number
Indicates that the receive data is data of the following block number groups. Receive Data DB2 DB1 0 0 1 1 0 1 0 1 Method B Receive data of block numbers 1 to 13 Receive data of block numbers 14 to 136 Receive data of block numbers 137 to 149 Receive data of block numbers 150 to 272 Method A Receive data of block numbers 1 to 60 Receive data of block numbers 61 to 130 Receive data of block numbers 131 to 190 Receive data of block numbers 191 to 272 (Method A0) Receive data of block numbers 191 to 284 (Method A1) (3) DB3: Block Synchronization Status
0: Indicates receive data in a block out-of-sync state 1: Indicates receive data in a block sync state (4) DB4: Parity Block Indication
This bit indication is available only in a frame synchronization state. 0: Receive data is not the data of the parity block. 1: Receive data is of the parity block.
5-4
(5)
DB5: Frame Synchronization Status Indication
0: Receive data is in a frame out of sync state. 1: Receive data is in a frame sync state. (6) DB6: CRC Result Indication
0: Indicates that the CRC result for the receive data is normal. 1: Indicates that the CRC result for the receive data is an error. (7) DB7: REAL Block Indication
This indication is used for receive block data in a frame sync state when frame A is set in the frame method register (01FH). 0: Receive data is not of the REAL block. 1: Receive data is of the REAL block.
5-5
5.2.2
Receive Data RAM Port
This port is used for one block receive data RAM of 34 bytes excluding BIC. When an interrupt occurs, the internal memory addresses are cleared to zero. Since the next receive data is output at the rising edge of an RD03 signal, 34 bytes can be read successively. The status of receive data is shown in 5.2.1. (1)
Address Read/write 003H Read
Reset value
DB7 b7
DB6 b6
DB5 b5
DB4 b4
DB3 b3
DB2 b2
DB1 b1
DB0 b0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
5.2.3
Receive RAM, Data Accumulation Condition, and Address Clear
(1) DB1: This register specifies the condition (frame/block synchronization) for accumulating data into the receive RAM. If any data is written to this register, the receive RAM addresses are cleared to zero. Write the following data before reading the receive RAM second time and thereafter. 0: Receive data is accumulated in receive RAM when the frame is synchronized. 1: Receive data is accumulated in receive RAM when the block is synchronized. However, when frame synchronization is entered, receive data is accumulated even if the block is out of sync. (1)
Address Read/write 004H Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 --
DB1 0
DB0 --
5-6
5.2.4
BIC Monitor
This register indicates the block indentification code (BIC) of the block receive data. (1) (2) DB1 0 DB0 0
Address Read/Write 007H (1) (2) Read
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 0
DB2: When BIC is detected, "1" is indicated. DB0 - DB1: The detected BIC is output as shown below. DB1 0 0 1 1 DB0 0 1 0 1 BIC number BIC 1 BIC 2 BIC 3 BIC 4
5-7
Serial receive data
Serial to Data receive parallel conversion Data read RD03
First horizontal error correction
34 Bytes RAM
Switching
34 Bytes RAM
Data bus
Error correction (vertical/horizontal)
Vertical error correction & second horizontal error correction
272 Bytes RAM
021H
Figure 5.2.1 Receive RAM Configuration
5-8
1 block Block No. Byte No. Interrupt Receive interrupt clear Receive Data (003H) N-1 block Receive data (34 bytes) Receive interrupt clear N-1 35 0 1 N 2 3 4 5 25 26 34 35 0 N-1 block receive interrupt N block receive interrupt N+1 1
DB0
N-1 block Frame No. change 00 01 10 11 Repeat
DB1, 2
N-1 block Frame No. N-1 block Block synchronous state Parity block: 1
5-9
Receive Block State (002H) BIC Monitor (007H)
DB3
DB4 DB5
N-1 block Parity block indication N-1 block Frame synchronous state Error: 1
DB6
N-1 block CRC result indication No error: 0
DB7 DB0, 1
N-1 block REAL block indication N-1 block BIC No.
Figure 5.2.2 Receive Data Timing Diagram
5.3 5.3.1
CLOCK REGENERATION REGISTERS Fixed Phase Adjustment
This register adjusts the phase of a 16 kHz data sampling clock in 1/125 steps within the range of -1/5 to +24/125. This register is used for initial settings. (3) (2) DB5 0 DB4 0 DB3 0 DB2 0 (1) DB1 0 DB0 0
Address Read/write 008H (1) DB2 0 0 0 0 1 1 1 1 Write
Reset value
DB7 --
DB6 0
DB0-DB2: Phase delay settings in 1/125 steps DB0 0 1 0 1 0 1 0 1 Phase Delay Setup Value 0/125 1/125 2/125 3/125 4/125 Inhibit Inhibit Inhibit
DB1 0 0 1 1 0 0 1 1
(2) DB5 0 0 0 0 1 1 1 1
DB3-DB5: Phase delay settings in 1/25 steps DB3 0 1 0 1 0 1 0 1 Phase Delay Setup Value 0/25 1/25 2/25 3/25 4/25 Inhibit Inhibit Inhibit
DB4 0 0 1 1 0 0 1 1
5-10
(3)
DB6: Phase advance setting in 1/5 steps
DB6 0 1
Phase Lead Setup Value 0 1/5
Receive data (MON pin) Data sampling clock (MOUT5 pin) LSB x0100100 x0000000 x1100100 x1000000 Figure 5.3.1 Phase Adjustment
5-11
5.3.2
Bit Gate
This register sets the gate width centered around the rising edge of the data clock. Gate width can be changed depending on parameters set before and after block synchronization. This function is for varying the constant of integration for the clock sampling timing detected inside and outside the gate. This register is used for initial settings. (2) (1)
Address Read/write 009H (1) (2) Write DB0-DB1: DB2-DB3:
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 0
DB2 0
DB1 0
DB0 0
Before block synchronization After block synchronization Before Block Synchronization DB1 0 0 1 1 DB0 0 1 0 1 Gate 0 Gate 1 Gate 2 Gate 3 10% 20% 30%
After Block Synchronization DB3 0 0 1 1 DB2 0 1 0 1
Gate
Receive data Data clock Gate 0 Gate 1 Gate 2 Gate 3 Clock sampling timing Figure 5.3.2 Clock Sampling Gate
5-12
5.3.3
Integration Constant
This register sets the timing sampling count required for phase control. The parameters are before and after block synchronization, and inside and outside the gate. This register is used for initial settings. (1) Integration constant before block synchronization, outside the gate (0-15) Reset value DB7 -- DB6 -- DB5 -- DB4 -- DB3 0 DB2 0 DB1 1 DB0 0
Address Read/write 00AH (2) Write
Integration constant before block synchronization, inside the gate (0-15) Reset value DB7 -- DB6 -- DB5 -- DB4 -- DB3 0 DB2 0 DB1 1 DB0 0
Address Read/write 00BH (3) Write
Integration constant after block synchronization, outside the gate (0-63) Reset value DB7 -- DB6 -- DB5 0 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
Address Read/write 00CH (4) Write
Integration constant after block synchronization, inside the gate (0-63) Reset value DB7 -- DB6 -- DB5 0 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0
Address Read/write 00DH Write
5-13
5.3.4
Phase Correction Step
This register sets the phase correction step width of DPLL used for data clock regeneration. This register can be used to adjust data clock supply speeds or data clock jitter control. Phase correction step widths can be changed depending on parameters set before or after block synchronization. This register is used for initial settings. (2) (1) DB2 1 b0 DB1 0 b1 DB0 1 b0
Address Read/write 00EH Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 0 b1
Time constants can be set as shown in Table 5.3.1 by combining the integration constants shown in Sections 5.3.3 and 5.3.4.
Table 5.3.1 Phase Correction Step Integration Constant bb 10 Phase Correction Step 1/ (= 0.4% = 4000 ppm) 4 MHz 0 0 Packet count required for a 1-bit phase displacement 2/ (= 0.8% = 8000 ppm) 4 MHz 0 1 Packet count required for a 1-bit phase displacement 4/ (= 1.6% = 16000 ppm) 4 MHz Packet count required for a 1-bit phase displacement 1 2 After Block Synchronization Before Block Synchronization 4 1000 ppm 2.77 Packet 8 500 ppm 5.55 Packet 16 250 ppm 11.1 Packet 32 125 ppm 22.2 Packet 64 62.5 ppm 44.4 Packet 125 ppm 22.2 Packet 250 ppm 11.1 Packet 4000 2000 ppm ppm 0.69 Packet 1.38 Packet
8000 4000 ppm ppm 0.34 Packet 0.69 Packet
2000 ppm 1.38 Packet
1000 ppm 2.77 Packet
500 ppm 5.55 Packet
250 ppm 11.1 Packet 500 ppm 5.55 Packet
1
0
16000 8000 ppm ppm 0.17 Packet 0.34 Packet
4000 ppm 0.69 Packet
2000 ppm 1.38 Packet
1000 ppm 2.77 Packet
1
1
5-14
5.4 5.4.1
BLOCK SYNCHRONIZATION REGISTERS Allowable Number of BIC Error Bits
This register specifies how many erroneous bits can be allowed in the block identification code (BIC). Values can be changed depending on parameter values before and after block synchronization. This register is used for initial settings. (2) (1) DB2 1 DB1 1 DB0 0
Address Read/write 010H (1) DB1 0 0 1 1 (2) DB3 0 0 1 1 Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 0
Allowable number of erroneous BIC bits before block synchronization DB0 0 1 0 1 Allowable Number of Erroneous Bits in BIC Before Block Synchronization 0 1 2 3
Allowable number of erroneous BIC bits after block synchronizaiton DB2 0 1 0 1 Allowable Number of Erroneous Bits in BIC After Block Synchronization 0 1 2 3
5-15
5.4.2
Number of Block Synchronization Backward Protection Steps
This register specifies the number of block synchronization backward protection steps. When block identification codes (BICs) are successively detected for a specified number of times, the internal bit counter and the bit position of the block (0-287) are synchronized. This register is used for initial settings. (1)
Address Read/write 011H (1) DB1 0 0 1 1 Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 --
DB1 0
DB0 1
DB0-DB1: Number of block synchronization backward protection steps DB0 0 1 0 1 Block proving in synchronization step count Inhibit 2 3 4
5.4.3
Number of Block Synchronization Forward Protection Steps
This register specifies the number of block synchronization forward protection steps. If BICs cannot be detected successively for a specified number of times after block synchronization, the block is regarded as out of synchronization. This register is used for initial settings. (1)
Address Read/write 012H (1) DB3 0 0 Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 1
DB2 0
DB1 0
DB0 0
DB0-DB3: Number of block synchronization forward protection steps DB2 0 0 DB1 0 0 DB0 0 1 Number of Block Synchronization Forward Protection Steps 0 (Inhibit) 1
1
1
1
1
15
5-16
5.4.4
Block Synchronization Monitor
(1) (2) Block synchronization monitoring register (DB0) Registers to monitor the number of block synchronization forward protection steps (DB4-DB7). Both (1) and (2) are used for testing. (2) (1) DB5 0 DB4 0 DB3 -- DB2 -- DB1 -- DB0 0 Reset value DB7 0 DB6 0
Address Read/write 013H (1) Read
DB0: Monitors block synchronization status. 0: block out-of-synchronization 1: block synchronized DB4-DB7: Monitors the number of block synchronization forward protection steps. While a block is synchronized, if a BIC is not detected in a number of successive attempts, the number of attempts is decremented from the set number of block synchronization forward protection steps; when all the values of DB4 to DB7 change from 1 to 0, it is judged that the block is out of synchronization.
(2)
DB7 0 0
DB6 0 0
DB5 0 0
DB4 0 1
Remaining Number of Block Synchronization Forward Protection Steps 0 1 Synchronization detection Out of synchronization When BIC cannot be detected
1
1
1
1
15 Load during synchronization
5-17
5.4.5
Block Synchronization Set
This register forcibly sets block synchronization, and is used for testing.
Address Read/write 014H Write
Reset value
DB7 x
DB6 x
DB5 x
DB4 x
DB3 x
DB2 x
DB1 x
DB0 x
x : don't care
5.4.6
Block Synchronization Clear
This register forcibly sets block out-of-synchronization. This setting is effective when a channel is changed, in clearing a previous synchronizing status, to permit faster synchronization for the new channel.
Address Read/write 015H Write
Reset value
DB7 x
DB6 x
DB5 x
DB4 x
DB3 x
DB2 x
DB1 x
DB0 x
x : don't care
5.4.7
Bit Number Monitor
These registers monitor bit numbers. They are used for testing. DB0 of the 017H register is MSB, and DB0 of the 016H register is LSB. Numbers 0 to 287 are displayed.
Address Read/write 016H Read
Reset value
DB7 0 b7
DB6 0 b6 DB6 --
DB5 0 b5 DB5 --
DB4 0 b4 DB4 --
DB3 0 b3 DB3 --
DB2 0 b2 DB2 --
DB1 0 b1 DB1 --
DB0 0 b0 DB0 0 b8
Address Read/write 017H Read
Reset value
DB7 --
5-18
5.5 5.5.1
FRAME SYNCHRONIZATION REGISTERS Number of Frame Synchronization Backward Protection Steps
This register specifies the number of times that synchronization points required for frame synchronization have to be detected in succession in order for the frame to be judged as being synchronized. When the block number changing points (= frame synchronization points: 272AE1, 13AE14, 136AE137, and 149AE150, under format B) are detected the same number of times as the specified number of successive steps (number of frame synchronization backward protection steps), frame synchronization is entered and the internal frame counter is synchronized with the detected block number. (1)
Address Read/write 018H Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 --
DB1 0
DB0 1
(1)
DB1 0 0 1 1
DB0-DB1: Number of frame synchronization backward protection steps
DB0 0 1 0 1 Number of Frame Synchronization Backward Protection Steps 1 2 3 4
5.5.2
Number of Frame Synchronization Forward Protection Steps
This register specifies the number of times that successive unsuccessful attempts to detect the synchronization points required for frame synchronization that will cause a judgment that a frame is out of synchronization. After frame synchronization, if the block number changing points (= frame synchronization points: 272AE1, 13AE14, 136AE137, and 149AE150, under format B) are not detected the same number of times as the specified number of successive steps (number of frame synchronization forward protection steps), the frame will be out of synchronization to terminate data reception. This register is used for initial settings. (1)
Address Read/write 019H Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 0
DB2 1
DB1 0
DB0 0
(1)
DB3 0 0 . . . . 1
DB0-DB3: Number of frame synchronization forward protection steps
DB2 0 0 . . . . 1 DB1 0 0 . . . . 1 DB0 0 1 . . . . 1 Number of Frame Synchronization Forward Protection Steps 0 (Inhibit) 1 . . . . 15
5-19
5.5.3
Frame Synchronization Monitor
(1) (2) Frame synchronization monitoring register (DB1) Register for monitoring the number of frame synchronization forward protection steps (DB4DB7) Both (1) and (2) are for testing. (2) (1) Reset value DB7 0 DB6 0 DB5 0 DB4 0 DB3 -- DB2 -- DB1 0 DB0 -- Read (1)
Address Read/write 01AH
DB1: Monitors frame synchronization status. 0: frame out-of-synchronization 1: frame synchronized DB4-DB7: Monitors the number of frame synchronization forward protection steps. While a frame is synchronized, when successive attempts to detect frame synchronization points fail, that number of attempts is decremented from the set number of frame synchronization forward protection steps; when all the values of DB4 to DB7 change from 1 to 0, the frame is judged to be out of synchronization.
(2)
DB7 0 0
DB6 0 0
DB5 0 0
DB4 0 1
Remaining Number of Frame Synchronization Forward Protection Steps 0 1 Synchronization detection
Out of synchronization When a frame synchronization point cannot be detected
1
1
1
1
15 Load when a synchronization point is detected
5-20
5.5.4
Frame Synchronization Set
This register forcibly sets frame synchronization and is used for testing.
Address Read/write 01BH Write
Reset value
DB7 x
DB6 x
DB5 x
DB4 x
DB3 x
DB2 x
DB1 x
DB0 x
x : don't care
5.5.5
Frame Synchronization Clear
This register forcibly sets frame out-of-synchronization. This function is effective when a channel is changed, in clearing a previous synchronizing status, to permit faster synchronization for the new channel.
Address Read/write 01CH Write
Reset value
DB7 x
DB6 x
DB5 x
DB4 x
DB3 x
DB2 x
DB1 x
DB0 x
x : don't care
5.5.6
Block Number Monitor
These registers monitor block numbers and are used for testing. DB0 of 01EH register is MSB, and DB0 of 01DH register is LSB. Numbers 0 to 271 are displayed.
Address Read/write 01DH Read
Reset value
DB7 0 b7
DB6 0 b6 DB6 --
DB5 0 b5 DB5 --
DB4 0 b4 DB4 --
DB3 0 b3 DB3 --
DB2 0 b2 DB2 --
DB1 0 b1 DB1 --
DB0 0 b0 DB0 0 b8
Address Read/write 01EH Read
Reset value
DB7 --
5-21
1 frame
1 frame
Block 1-13
Block 14-136
Block 137-149
Block 150-272
Receive frame (synchronization detection points A, B, C and D) A B C D A B C D E
Start F BIC (Block Identification Code) detection 18 ms 2 = 36 ms Block synchronizing signal
18 ms 7 = 126 ms 8 continuous BICs not detected. G
5-22
3 continuous BICs detected.
Frame identification code detection 2.44 seconds Frame synchronizing signal 3 continuous frame identification codes detected. (BIC change points D, A, and B detected.) 3 continuous frame identification codes not detected. (BIC change points C, D, and E detected.) 2.44 seconds
The frame synchronization time can become a maximum depending on the detection position; for example, the time between BCs, 2.21 seconds, is added to make it 4.65 seconds (the same is true for out-of-synchronization). (Note) This figure is an example under frame format B. Figure 5.5.1 Block and Frame Synchronization
5.5.7
Frame Format Specification
Reset value DB7 -- DB6 -- DB5 -- DB4 -- DB3 -- DB2 -- DB1 1 DB0 0
Address Read/Write 01FH Write
B1 0
B0 0
Frame Format Format A
Symbol A0
Note -- Including realtime information block.
Japan, FMSS
0
1
A1
1 1
0 1
Format B Format C
B C
--
5-23
5.6 5.6.1
ERROR CORRECTION REGISTERS Internal Memory Address Counter Clear
This command clears the address counter of internal memory (set to 0) before writing and reading an error correction data block. Since error correction is executed sequentially from address 0 of internal memory, the internal memory address counter must be cleared before writing. After error correction, it is necessary to clear the internal memory address counter to read data sequentially from address 0 of internal memory.
Address Read/write 020H Write
Reset value
DB7 x
DB6 x
DB5 x
DB4 x
DB3 x
DB2 x
DB1 x
DB0 x
x : don't care
5.6.2
Data Transfer Port for Error Correction
This port writes data before error correction and reads data after error correction. When correcting an error in a horizontal (vertical) direction after clearing the internal memory address counter, write 34 (272) bytes of data to this port. After correcting an error in a horizontal (vertical) direction, clear the internal memory address counter, then read 34 (272) bytes of data from this port. When reading or writing data for this port, it is unnecessary to specify the horizontal (vertical) direction error correction mode.
Address Read/write 021H Read/write
Reset value
DB7 b7
DB6 b6
DB5 b5
DB4 b4
DB3 b3
DB2 b2
DB1 b1
DB0 b0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
5-24
5.6.3
Error Correction Start Signal
When start action specification data is written into DB0 to DB2, error correction starts in the specified mode. When error correction is completed, an interrupt is generated. The operation status of the error correction circuit can be monitored by this register. (2) Read (1) Write
Address Read/write 022H Read/write
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 0
DB1 0
DB0 0
(1) DB0 - DB2 (Write) DB2 0 DB1 0
: Error correction start mode specification DB0 1 Start Action (write) Horizontal error correction of receive block data (at address 003H on the 34-byte RAM) starts. Corrected data is written toaddress 003H on the RAM.
0
1
0
Vertical error correction of data written in address 021H on the 272-byte RAM starts. Corrected data is written in address 021H on the RAM.
1
0
0
Horizontal error correction of data written in address 021H on the 34-byte RAM starts. Corrected data is written in address 021H on the RAM.
(2) DB0 - DB2 (Read)
: Monitor
The data written in this register can be used to monitor the error correction circuit operation status because the data is cleared after error correction is complete. DB0: Displays the operation status of the horizontal error correction for receive block data. DB1: Displays the operation status of the vertical error correction. DB2: Displays the operation status of the 2nd horizontal error correction. for each of these bits: 0: Error correction circuit is idle. 1: Error correction circuit is in operation.
5-25
5.6.4
CRC Result Indication
This register indicates a 14-bit CRC result. When horizontal direction error correction is executed, a 14-bit CRC is performed internally on corrected data and the result is indicated. This register is cleared immediately after error correction starts. (1)
Address Read/write 023H Read
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 --
DB1 --
DB0 0
DB0: 14-bit CRC result 0: Normal 1: Error
5.6.5
Error Correction Result Indication
This register indicates an error correction result. If syndrome registers are all 0 after error correction, this register indicates a normal status. If not, it indicates an error. This register is cleared immediately after error correction starts. In the case of a horizontal-direction correction, the result is indicated at DB7. In the case of a vertical-direction correction, the result is indicated at DB0-DB7 corresponding to bits 0-7. (2) (1)
Address Read/write 024H (1) Read
Reset value
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
DB7: Horizontal-direction error correction result 0: Normal 1: Error DB0-DB7: Vertical direction error correction result (corresponding to bits 0-7) 0: Normal 1: Error
(2)
5-26
5.6.6
Majority Logic Threshold Value
This register sets the majority logic threshold value for error correction. The setup range is 1 to 17. This register is used for initial settings.
Address Read/write 025H DB4 0 0 Write DB3 0 0
Reset value DB2 0 0
DB7 -- DB1 0 0
DB6 -- DB0 0 1
DB5 --
DB4 0
DB3 1
DB2 0
DB1 0
DB0 0
Majority Logic Threshold Value Inhibit 1
~
~
~
~
~
0
1
0
0
0
~
~
~
~
~
0 1 1
1 0 0
1 0 0
1 0 0
1 0 1
5.6.7
Internal Address Monitor
This register indicates the addresses (0-271) of internal memory for error correction. This is used for testing. (1)
Address Read/write 026H Read
Reset value
DB7 0 b7
DB6 0 b6
DB5 0 b5
DB4 0 b4
DB3 0 b3
~
15 16 17 DB2 0 b2 DB1 0 b1
~
8
DB0 0 b0
Address Read/write 027H Read
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 --
DB1 --
DB0 0 b8
5-27
* *
Error correction involves external RAM, a microcontroller and MSM9552/9553. Transfer data in error correction units (horizontal direction equals 34 bytes, vertical direction equals 272 bytes) from external memory to the internal buffer of the MSM9552/9553. Error correction is then executed. Transfer data after error correction from the internal buffer to external memory.
External memory Data bus
MSM9560/9561 Internal data buffer Error correction
Microcontroller
Figure 5.6.1 General Configuration of Error Correction
Error correction start Address generation
CRC result
Address bus Data bus WR RD Note: CRC is executed on data after horizontal-direction error correction. Figure 5.6.2 Configuration of Error Correction Section Bus IF Internal RAM 272W 8 bits PAES PS Error correction 14-bit CRC
5-28
Internal data memory address b7 00 01 Bit No. b0
Internal data memory address b7 00 01 Bit No. b1 b0
(Error correction execution sequence)
(Error correction execution sequence)
21 22 Parity 33 Error correction is executed for each bit of bit 0 to bit 7, from byte 0 to byte 271.
189 190 Parity block
271 Horizontal direction error correction Eight times Vertical-direction error correction
Figure 5.6.3 Error Correction Sequence
5-29
Internal memory address clear Address bus 020H
Data write 021H
Error correction start 021H 022H
Error correction
INT read (Error correction end) INTCLR
Error Internal memory CRC correction result result address read read clear
Data read
000H 000H 020H 023H 024H 021H Don't DB3 = 1 DB3 = 1 care DB0 = 0 DB0-7 = 0 Data 0
Data 33 read 021H
Data Data bus 0
Data 1
Data
Data 33
Start signal FF
Data
Data Data 33
WR RD 250 ns or longer 022H, DB1, 2 INT pin Error correction period
274 ms/1 horizontal block (34 bytes)
50 ns or longer
5-30
600 ns or less Null Operating
INTCLR, 250 ns or longer
Internal memory address (Note 1, 2, 3)
0
1
32
33
2178 ms/1 vertical block (1 byte 272 words) 0 33
34
0
1
33
Note 1: Internal memory address is incremented by RD or WR ( ). Note 2: Internal memory address counter is automatically cleared only when error correction starts. Note 3: Internal memory address can be monitored. (The address is the one to be read/written the next time.) Figure 5.6.4 Error Correction Timing Diagram
5.7 5.7.1
LAYER 4 CRC REGISTERS Layer 4 CRC Register Clear
This command clears the CRC register and sets all of its contents to 0 before layer 4 CRC processing. Execute this command once before reading the data group on which CRC processing is to be performed.
Address Read/write 028H Write
Reset value
DB7 x
DB6 x
DB5 x
DB4 x
DB3 x
DB2 x
DB1 x
DB0 x
x : don't care
5.7.2
Layer 4 CRC Data Buffer
Write the data group on which CRC processing is to be performed in byte units with a cycle of 4.5 s or longer. The data written inside the IC is loaded to the CRC operation register and a shift operation is executed (eight times). The system then waits for the next data input.
Address Read/write 029H Write
Reset value
DB7 0
DB6 0
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
5.7.3
Layer 4 CRC Result Indication
This register indicates a layer 4 CRC result. After the last data of a data block is written, pause for at least 4.5 s before reading. (1)
Address Read/write 02AH (1) Read
Reset value
DB7 --
DB6 --
DB5 --
DB4 --
DB3 --
DB2 --
DB1 --
DB0 0
DB0: layer 4 CRC result 0: Normal 1: Error
5-31
5.7.4
Layer 4 CRC Register
This register is used for writing initial values directly to the CRC operation register , and reading values which are still in progress. With this function, layer 4 CRC processing for multiple data groups can be performed in parallel. For example, CRC processing for a short data group can be inserted while CRC processing for a long data group is in progress. (1) Layer 4 CRC register high-order 8 bits Reset value DB7 0 b7 (2) DB6 0 b6 DB5 0 b5 DB4 0 b4 DB3 0 b3 DB2 0 b2 DB1 0 b1 DB0 0 b0
Address Read/write 02BH Read/write
Layer 4 CRC register low-order 8 bits Reset value DB7 0 b15 DB6 0 b14 DB5 0 b13 DB4 0 b12 DB3 0 b11 DB2 0 b10 DB1 0 b9 DB0 0 b8
Address Read/write 02CH Read/write
5-32
Data bus DB0-DB7 DB0 RD2B RD2C RD2A
WR29
Load
P
S
CRC register (high-order 8 bits) WR2B
CRC register (low-order 8 bits) WR2C
All 0 detection
Shift clock generation (8) CLR WR28 CRC clear 028H CRC clear FF
Shift CK
Data load 029H Data 0 Data 1 Data n-2 029H Data n-1
Address bus
CRC result read 02AH DB0 = 0
Data bus
WR RD Write data at time intervals of 4.5 ms or longer 4.5 ms or longer
Figure 5.7.1 Layer 4 CRC Block Diagram and Timing Diagram
5-33
5.8
ANALOG SECTION CONTROL/MONITOR REGISTER
This register is used for level adjustment of the analog input signal (composite signal) and analog section test mode settings. (3) (2) (1)
Address Read/write 030H (1) Write
Reset value
DB7 --
DB6 --
DB5 0
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
DB0: DETC Controls the input of analog input pin ADETIN. 0: Disables the input of analog input pin ADETIN, so that the input buffer amplifier is powered down (during FM multiplex broadcast reception). 1: Enables the input of analog input pin ADETIN, so that the input buffer amplifier is powered on. The connections are switched as follows (available for input of a 16 kbps digital test signal) : DB0 AIN pin Filter
Internal delay detection circuit
0 1 ADETIN pin Input buffer amplifier
Data discrimination circuit (DET)
Figure 5.8.1 Switching Analog Input Pins (2) DB1-DB2: SGAIN0, SGAIN1 This register is used for gain switching for the variable gain amplifier for analog input signal. These signals are used for initial settings. Set the values of DB1 and DB2 so that the following expression is satisfied: Peak value of the analog input signal (composite signal) gain = 1.5 to 2.0 VP-P (MSM9552) = 0.5 to 0.9 VP-P (MSM9553) This is effective for improving the S/N ratio. SGAIN0 DB1 0 1 0 1
SGAIN1 DB2 0 0 1 1
Gain 1 1.5 2 3
5-34
(3)
DB3-DB5: M0-M2 Monitors internal filter output waveforms and controls MON pin (pin 1) output. Refer to Figure 5.8.2 for the part that can be monitored. After clear, the internal MON amplifier is powered OFF and the output becomes high impedance. (M1) DB4 0 0 1 1 0 0 1 1 (M0) DB3 0 1 0 1 0 1 0 1 MON Pin (pin 1) Output Internal monitor amplifier power off, high impedance output q LPF output of input stage w BPF internal waveform 1 e BPF internal waveform 2 r BPF internal waveform 3 t BPF output y Internal amplifier output u Delay detection output
(M2) DB5 0 0 0 0 1 1 1 1
5-35
q Input-stage LPF output
w e r t
BPF internal waveform 1 BPF internal waveform 2 BPF internal waveform 3 BPF output y Internal Amp output
AIN
LPF
Variable gain AMP
BPF (SCF)
Limiter
Amp
+ -
Vref SG Filter Section
1T delay circuit
+
LPF
+ - Limiter
To digital signal processor
Delay Detection Section
u Delay detection output Figure 5.8.2 Analog Section Output Waveform Monitor
5-36
5.9
POWER DOWN CONTROL REGISTER
This is a power down setting register. (4) (3) DB4 0 DB3 -- DB2 0 (2) DB1 0 (1) DB0 0
Address Read/write 031H (1) Write
Reset Value
DB7 --
DB6 0
DB5 0
DB0: Analog section power down control 0: Power down (operation stops). 1: Power on (after power is turned on, several milliseconds are necessary until the circuit stabilizes). DB1: Digital section power down control 0: The digital section is power down, and the internal clock stops. Since the clock stops at "H", operation can be continued after power on. 1: The digital section is power on. Operation starts from clock "H". External oscillation control When input pin XOUTC = "1", operation of crystal oscillation circuits (XTAL1, XTAL2) is controlled as described below. The output pin XOUT is fixed to "L". 0: Stops the operation of the crystal oscillation circuits. 1: Starts the operation of the crystal oscillation circuits. When input pin XOUTC = "0", the crystal oscillation circuits (XTAL1 and XTAL2) are always in an oscillation state, and the output pin XOUT always outputs oscillation clocks. Dividing of external clock (XOUT) The divided clocks to the XOUT pin are set up. DB2:
(2)
(3)
(4)
DB6 (XCK2) 0 0 0 0 1 1 1 1
DB5 (XCK1) 0 0 1 1 0 0 1 1
DB4 (XCK0) 0 1 0 1 0 1 0 1
Clock XOUT pin 8.192 MHz 4.096 MHz 2.048 MHz 1.024 MHz 0.512 MHz 0.256 MHz 0.128 MHz 0.064 MHz
5-37
XTAL1
XTAL2
DB2 WR31 CLR
D Q
CK
Frequency Divider XOUT
XOUTC Figure 5.9.1 Oscillator Circuit Control
5-38
5.10
TEST CONTROL REGISTERS
5.10.1 Test Control 0
This register controls switching of the test pins (MOUT0-MOUT4). (1) Address Read/write 032H (1) Write DB5-DB7: Reset value DB7 0 DB6 0 DB5 0 DB4 -- DB3 -- DB2 -- DB1 -- DB0 --
See Table 5.10.1 for details.
5.10.2 Test Control 1
This register controls the decoding mode of serial receive data and test switching. (5) Address Read/write 033H (1) Write Reset value DB7 -- DB6 0 DB5 0 (1) DB4 0 (4) DB3 0 (3) DB2 0 (2) DB1 0 (1) DB0 0
DB0, DB4: Serial receive data output Outputs serial receive data (serial receive data converted by the control in (3) to (5) below) to MOUT6 pin. The output data changes at the rising edge of a 16 kHz regeneration data clock (MOUT5 pin). DB0 0 1 0 1 Fixed to "L" Serial receive data after descrambling Serial receive data before descrambling MOUT 6 Pin Output
DB4 0 0 1 1 (2)
DB1: 16 kHz regeneration data clock A 16 kHz regeneration data clock is output to the MOUT5 pin. 0: MOUT5 Pin is fixed to "L". 1: A 16 kHz regeneration data clock is output to the MOUT5 pin. DB2: Differential decoding control 0: Performs differential decoding to input data. 1: Does not perform differential decoding. (In FM multiplex broadcast, differential decoding is not used, so use DB2 = "1".) DB3: Descrambler (regeneration of dc component of data) control 0: Descrambles input data other than BIC. (This is used for receiving FM multiplex broadcast.) 1: Does not descramble. (This is used for testing.)
(3)
(4)
5-39
(5)
DB5, DB6: Delay detector output control
Delay Detector Control
DB6 0 0 1 1
DB5 0 1 0 1
(controls input data and data before 1T)
Purpose of Use FM multiplex broadcast reception For testing
ENOR Through (data before 1T) EOR
5-40
Table 5.10.1 Monitor Input/Output Pins
Test Control 0 Test Control
Address = 032H (DB7, DB6, DB5) Extension Port LSI Internal Signal Monitor (Note) TST0 (001) TSTTI (010) TSTB0 (011) TSTB1 (100) TSTC (111) *1 *2 *3 *3 (Note) Since the LSI internal signal monitor is normally used for LSI device shipment inspection, the user does not have to use it, but the items *1 to *4 below can be monitored. *1 FSYNC AE Frame synchronizing state "0": out of shnchronizing "1": synchronizing *2 BSYNC AE Block synchronizing state "0": out of shnchronizing "1": synchronizing *3 BIC0, BIC1 AE BIC number indication BIC0 BIC1 0 0 1 0 BIC2 0 1 BIC3 1 1 BIC4 TS11 TS21 TS10 GATE PHCK1 FRCK0 FRCK1 FRCK2 FRCK3 BCK FSYNC BSYNC RAMOUT BICDET2 BICDET
Pin Name
Pin No. I/O
(110) (101) (000)
MOUT0 MOUT1 MOUT2
8 9 10 11 12
0FH register BPF limmiter Output output DB0 0FH register Delay detection Output output DB1 Output Output Output 0FH register DB2 DB3 0FH register DB4 DET output
BIC0 BIC1
5-41
MOUT3 MOUT4
0FH register SCF clock output Fixed to "L"
*4 BICDET1
BIC No. BIC1
Test Control 1
*4 BICDET1 AE BIC detection state "0": detecting NG "1": detecting OK Test control 1
Pin Name
Pin No. I/O
Address = 033H Test Control 1 DB1 0 1 CK16K -- Test control 1 DB0, DB4 DB0 DB4 0 0 -- Fixed to "L" 1 0 -- Serial receive data 0 1 -- Serial receive data 1 1
MOUT5 MOUT6
13 14
Output Fixed to "L" Output --
after descrambling before descrambling
5.11
I/O ADDRESS REGISTER
This register sets up an internal register address irrespective of pins A0 to A5. The address set up by this register becomes valid when IOEN (DB7) is set to "1". When CS = "1" and IORD = "0", data in the internal register is output onto the data bus. When CS = "1" and IOWR = "0", data on the data bus is written in the internal register. (1) (2) DB6 -- DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
Address Read/write 037H (1) Write DB7: IOEN
Reset value
DB7 0
0: Address set up by this register is invalid. 1: Address set up by this register is valid as an internal address in the IC. (2) DB0 - DB5: Corresponds to external addresses A0 to A5.
5-42
5.12
EXTENDED PORT REGISTER
Data (B0 to B4) in this register is output to the monitor output pins MOUT0 to MOUT4 by writing 000xxxxx, 101xxxxx, or 110xxxxx to the port mode register (032H). Refer to the table 5.10.1.
Address Read/write 00FH Write
Reset value
DB7 --
DB6 --
DB5 --
DB4 0
DB3 0
DB2 0
DB1 0
DB0 0
Usage example of the extended port When the clock of the microcomputer that controls the MSM9552/9553 is supplied from the XOUT pin of the MSM9552/9553, the following two problems will occur: 1. When used with XOUTC = "1" When this register is cleared, the microcomputer does not operate, because the XOUT pin is fixed at "L". 2. When used with XOUTC = "0" When this register is cleared, oscillation does not stop even in the power down mode, because the XOUT pin always outputs clock. The above troubles are cleared up using the extended port function. By connecting the XOUTC pin and MOUT0 pin externally as shown below, XOUTC goes to "0" and XOUT pin outputs the clock, after clear. By writing DB0 of 00FF to "1", XOUTC is set to "1", during power down mode. As a result, oscillation does not stop during clear, and can be stopped by the software only during power down mode.
7
MOUT0 8 Connect XOUTC and MOUT0 externally.
Figure 5.12.1 Usage Example of Extended Port
XOUTC
5-43
5-44
Chapter 6
EXTERNAL CONNECTION EXAMPLE
6.
MSM9552
Microcontroller interface +5 V power input 1 MON ADETIN (Note 3) AVDD + - DVDD 2
(Note 1)
DGND AGND 8.192 MHz crystal
CLR A5 A4 A3 A2 A1 A0 XOUT CS XTAL2 30 15 pF
40 38 37 36 35 34 33 32 31
Tuner part 6 AIN XTAL1 SG DVDD DGND 3 AVDD 27 + - 2.2 mF (Note 2) 28 (Note 3) 29 5
(10%) 330 pF
EXTERNAL CONNECTION EXAMPLE
(Note 2) 2.2 mF + - (Note 4)
6-1
4 AGND XOUTC 41 42 43 44 IORD IOWR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RD WR INT MOUT6 MOUT5 MOUT4 MOUT3 MOUT2 MOUT1 MOUT0 (Note 1) (Note 2) (Note 3) (Note 4) 26 25 24 23 22 21 20 19 18 16 15 14 13 12 11 10 9 8
(Note 3)
(Note 2) 2.2 mF + -
(Note 4) 7 17 39
This pin should be disconnected easily with a cutter for a failure analysis. Use a tantalum electrolytic capacitor. Separate the analog power pin (AVDD) and the digital power pin (DVDD). Make the analog ground pin (AGND) and the tuner ground common.
6-2
Chapter 7
APPLICATION CIRCUIT
7. APPLICATION CIRCUIT
MSM9552 FM tuner FM multiplex data demodulating IC 8 bits LCD control driver Buffer RAM Font ROM
MCU CPU
7-1
Sixteen kanji characters 2 lines LCD display
ROM
7-2
APPENDIX
APPENDIX: INTERNATIONAL FRAME FORMAT (ITU-R Rec. BS1194)
1) Format A0: Frame according to method A, without insertion of real time blocks.
~
BIC3 60 Blocks Information
~
BIC2 70 Blocks Information CRC Horizontal Parity
~
BIC1 60 Blocks Information
82 Blocks
~
BIC4 Vertical Parity
2) Format A1: Frame according to method A, with Static insertion of real time blocks.
~
BIC3 60 Blocks Information
~
BIC2 70 Blocks Information CRC Horizontal Parity
~
BIC1 60 Blocks Information
~
BIC4 4x BIC2 ~ BIC4 82 +12 Blocks 4x BIC2 ~ BIC4 4x BIC2 ~ BIC4 Real Time Information Block Real Time Information Block Real Time Information Block
Vertical Parity CRC Vertical Parity CRC Vertical Parity CRC Vertical Parity Parity Parity Parity
Appendix-1
3) Format B: Frame according to method B, with block interleave. BIC1 ~ 13 Blocks BIC1 BIC3 BIC3 BIC4 BIC3 BIC3 123 Blocks BIC4 BIC3 ~ BIC4 BIC3 BIC3 BIC4 BIC2 ~ 13 Blocks BIC2 BIC3 BIC3 BIC4 BIC3 BIC3 123 Blocks BIC4 BIC3 ~ BIC4 BIC3 BIC3 BIC4 Information 1 ~ Information 13 Information 14 Information 15 Parity 1 Information 16 Information 17 Parity 2 Information 18 ~ Parity 40 Information 95 Information 96 Parity 41 Information 97 ~ Information 109 Information 110 Information 111 Parity 42 Information 112 Information 113 Parity 43 Information 114 ~ Parity 81 Information 189 Information 190 Parity 82 CRC CRC Parity Parity CRC ~ Parity ~ Parity CRC CRC Parity Parity CRC ~ CRC CRC CRC Parity Parity Parity Parity ~ CRC CRC Parity Parity CRC ~ Parity ~ CRC CRC Parity Parity CRC ~ CRC CRC CRC Parity Parity Parity Parity ~
4) Format C: Frame according to method C, block code only. BIC3 Information CRC
Appendix-2

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